Integrated sub-micron vacuum gaps in semiconductor devices

Simulation Study of Deep Sub-micron and Nanoscale Semiconductor Transistors

CMOS Semiconductor Manufacturing Integration on Sub-micron Gate Spacer

This paper describes the details of a novel manufacturing process integration of CMOS (Complementary Metal-Oxide-Semiconductor) transistor architecture, which is incorporated into a sub-micron logic technology on 300mm wafers. As the gate length is scaling down, the spacer design for CMOS transistor becomes increasingly important especially for high performance. Experimental manufacturing proce...

Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design

Several regular circuit structures are proposed. They provide alternatives to the widely used standard-cell structure and have better predictability and a simpler design methodology. A regular global routing scheme is developed. A design flow for use with of all these regular fabrics is discussed.

Oxynitride Gate Dielectrics for Deep Sub-micron MOS Devices

The continuous demand for improved CMOS transistors necessitate smailer device dimensions. The reduction in chip size into the deep sub-micron dimensions opens up new scientific and engineering challenges. One of the most critical material in developing deep sub-micron MOS transistors is high quality ultrathin (a few nm) gate dielectric film. As the gate dielectric thickness is reduced to below...

Numerical analysis of deep sub-wavelength integrated plasmonic devices based on Semiconductor-Insulator-Metal strip waveguides.

We report the first study of nanoscale integrated photonic devices constructed with semiconductor-insulator-metal strip (SIMS) waveguides for use at telecom wavelengths. These waveguides support hybrid plasmonic modes transmitting through a 5-nm thick insulating region with a normalized intensity of 200-300 μm(-2). Their fundamental mode, unique transmission and dispersion properties are consis...